(1) Field of the Invention
The present invention relates in general to semiconductor voltage generator circuits, and particularly to capacitive voltage multiplier circuits using MOS transistors, even more particularly to voltage multiplier circuits using charge pumps manufactured as semiconductor integrated circuits.
(2) Description of the Prior Art
Recent developments in electronic devices for modern mobile and portable equipment for telecommunications and data processing have strengthened a tendency to an ever-continuing decrease of the applied supply voltages and furthermore to prefer components still needing one single supply voltage only. Portable devices are in general powered by batteries and weight and size of modern batteries play an important role in customer's acceptance, thus smaller devices with small batteries however furnishing low voltages only are in focus of current manufacturing and marketing strategies. Most modern integrated circuits utilizing a single power supply voltage incorporate on-chip circuitry to generate a “boosted” voltage having a magnitude greater than their own power supply voltage. Frequently this boosted voltage is used as a veritable power supply voltage for portions of the circuitry also contained on the integrated circuit and needing such higher voltages for their proper functioning. Common examples for integrated circuits comprising such portions are semiconductor memory devices of all kinds, such as Random Access Memory (RAM) circuits or special Non Volatile (NV)—RAM devices, like memory devices which make use of so-called ‘floating gates’ needing high voltages for their operation, like Flash-EPROM (Erasable Programmable Read-Only Memory) or E-EPROM (Electrically Erasable PROM) devices. Modern integrated memory devices using Magnetoresitive (MRAM) and Ferroelectric (FRAM) technologies are to be counted in also. Other types of circuits, e.g. for logic functions like EPLD (Erasable Programmable Logic Device) make also use of ‘floating gates’ and therefore need much higher voltages as their supply voltage VDD. Unlike many older devices, which required that two different power supply voltages be supplied, to operate the device (e.g., +5 and +12 volts), many contemporary devices now have only one single power supply voltage (usually called VDD: D as legacy from Drain) of (2.5-3.3) volts (relative to “ground” or VSS: S as legacy from Source). This VDD power supply voltage is typically utilized to power most of the device, within semiconductor memory devices also including the normal data read operation circuit parts. The higher voltage (frequently called VPP: P as legacy from Programming) is generated by an on-chip voltage generator having a typical value of +8 volts (again relative to VSS) rather than requiring a separate power supply voltage used for write operations within memory circuits. In many integrated circuits, such on-chip voltage generators are implemented as capacitive voltage multiplier circuits, largely because of the relative ease of implementing suitably large capacitors in a monolithic integrated circuit technology. These capacitive voltage multiplier circuits are usually called “charge pumps”. Charge pumps are circuits that pump charge into capacitors to develop an output voltage higher than the supply voltage. Such voltage generators or voltage multipliers used to “pump” a voltage from a lower voltage level to a higher voltage level are well known. Typically, they are used in non-volatile memory arrays in which the high voltage is required to program or erase the non-volatile memory cells. The supplied voltage is the “low” voltage and the “high” voltage is used to program or erase the memory cells. In general, electronic devices built as integrated circuits for a capacitive voltage multiplier operation are made up of multiple stages essentially connected in series and comprising charge pumps in order to “pump” a voltage from a lower source level to a higher source level. Many charge pump circuit stages can thus be implemented serially to increase the voltages provided. Each stage contains a pair of diodes (or transistors configured as a diode) and two capacitors. The stages are driven by a pair of alternating clock signals. High voltage charge pumps are able to provide positive or negative high voltages.
FIG. 1A prior art shows the three (3)-stage design of a prior art single anti-phase clock voltage multiplier circuit. This circuit displays said serial connection of Charge Pump stages (CP/CPs) built with easy integrable components only: MOS transistors and MOS capacitors, whereby each MOS transistor is connected in a diode configuration and also each capacitor is implemented by a MOS transistor. Each CP-stage is comprised of two serially connected Charge Transfer stages (CT/CTs) e.g. CTs1 (11) and CTs2 (12). Each CT stage is made up of one diode connected MOS transistor, e.g. D1 (14a) or D2 (14b) and one charge storage MOS capacitor, e.g. C1 (13a) or C2 (13b). Each CT stage has input node and output node, e.g. CTs1 nodes N1 (24) and N2 (26), CTs2 nodes N2 and N3 (28) respectively. The above-mentioned stage count of three for the circuit is based on this definition. The exemplary CP-stage 10 shall thus be consisting of diodes D1 and D2 and its two corresponding capacitors C1 and C2 as first stage 10. Capacitors C1 and C2 supply the two complementary control (clock) signals BSTA (25a) and BSTB (25b) to nodes N1 and N2 respectively, whereby all odd numbered (or alternately even-numbered) CT stages are supplied by BSTA and all even numbered (or alternately odd-numbered) CT stages by BSTB, which is clocked in anti-phase to BSTA. The abbreviation BST shall hereby remind of BooST, the action which is crucial for the circuit and which gets controlled by these signals, the letters A and B are used persistently to designate complementary pairs of items. An input isolation diode DVDD (18) feeds supply voltage VDD at node NVDD (20) to input node N1 connected to D1 and C1. Output node N3 connected to D2 leads eventually to the following CP-stages, in our case however only one further CT stage is following, namely CTs3 (17), set-up by MOS capacitor C3 (15) and diode connected MOS transistor D3 (16), whereby capacitor C3 is again supplying said clock signal BSTA to one electrode of diode D3. The other electrode of said diode D3 is now furnishing the output voltage VPP 29 of the multiplier circuit to a final load capacitor Cload 19, also connected to VSS 28 or ground. For future reference: the voltages at the individual nodes 24, 26 and 28 corresponding to the diode-capacitor combinations D1-C1, D2-C2 and D3-C3 shall be designated as V1, V2 and V3 respectively. The drawing in FIG. 1A prior art shows a so-called Dickson CP circuit proposed by J. Dickson in IEEE Journal of Solid-State Circuits (see J. F. Dickson, “On-Chip High-Voltage Generation in MNOS Integrated Circuits Using an Improved Voltage Multiplier Technique”, IEEE J. of Solid-state Circuits, vol. SC-11, No. 3, June, 1976, pp. 374-378, which is hereby incorporated by reference in its entirety). Dickson's architecture is a construction of diode-coupled switches and pumping capacitors responding to two complementary clock signals.
Referring now to FIG. 1A prior art again for a summary, the voltage multiplier circuit includes a plurality of serially connected CP-stages, one of which is labeled 10. Each CP-stage includes two CT stages, each made up of a diode D1 or D2 as charge transfer switch and a capacitor C1 or C2 as charge storage device, thus forming CTs1 and CTs2, each having an input node and an output node with corresponding voltages V1 at node N1, V2 at node N2 and V3 at node N3. A complementary pair of clock signals BSTA and BSTB is provided to drive the various pump stage capacitors C1 and C2. The input node N1 of the first serially-connected CP-stage is usually connected to the VDD power supply (at least for generating a boosted positive voltage) via an isolation diode DVDD, which may also be considered as part of another serially-connected CT stage, and the output voltage being VPP of the last CT stage, here CTs3, taken from output node NVPP (29) (which could otherwise be considered as output node of a last serially-connected CT stage) and measured over load capacitor Cload versus VSS or ground. Not previously mentioned are second order or side effects such as forward diode drop voltages or threshold voltages (V.sub.th) of the MOS-transistor diodes and parasitic stray capacitances (C.sub.s) formed in MOS circuits from said transistor drain and storage capacitor nodes versus ground. In practice, the diodes are frequently implemented as diode-connected MOSFETs, each with its gate terminal and drain terminal connected together to form one terminal of the diode, and its source terminal forming the other terminal of the diode. Also, the capacitors are frequently implemented as large area MOSFETs, each with its source terminal and drain terminal connected together to form one terminal of the capacitor, and its gate terminal forming the other terminal of the capacitor. Furthermore, the output voltage is usually somewhat less than this theoretical value, due to said stray capacitances, incomplete charge transfer, DC current flow provided into the output node, and other effects, which have been well studied in the literature and which shall be re-examined later. These have to be considered however in more detail because it is well known that voltage multiplier circuits based on Dickson's architecture fail to provide sufficient pumping efficiency when the power supply voltage VDD becomes very low, in which case their output gains for boosting voltages decrease to an unusable condition.
A time diagram of the anti-phase control clock signal of the circuit shown in FIG. 1A prior art is depicted in FIG. 1B prior art, displaying the voltage VBST for the two complementary clock signals BSTA and BSTB as a function of time t. These complementary control clock signals are usually driven with full VDD-level swings (i.e., transitioning between a low level of VSS and a high level of VDD). Consequently, each CP-stage boosts the voltage conveyed to its input node by an amount equal to VDD less a diode drop (assuming relatively negligible DC load current and ignoring second order effects).
In such a design the output voltage VPP 29 measured versus ground (VSS) is determined by the following equation, generalized for M stages and assuming no current load is required from the load capacitor Cload at output node 29:VPP=(VDD−V.sub.th)+M*(VBST*C/(C+C.sub.s)−V.sub.th)wherein:(VDD−V.sub.th) is the voltage at the input node N1 to the first CT or CP-stage of the voltage multiplier after the voltage has passed through the transistor DVDD, configured as diode;(V.sub.th) is the threshold voltage or forward diode drop voltage of each diode connected MOS transistor D(2n−1) and D(2n) in the multiplier; C is the capacitance of the coupling storage MOS capacitors C(2n−1) and C(2n) in the nth CT stage of the multiplier, with C(2n−1)=C(2n);(C.sub.s) is the stray capacitance versus ground (VSS) at the drain-capacitor node of each diode connected MOS transistor D(2n−1) and D(2n) in the multiplier; VBST is the voltage of the clock signals BSTA and BSTB, normally equaling VDD; M is the total number of stages of the multiplier; and n is a running index (1 . . . M). Typically, C/(C+C.sub.s) is about 85% and (V.sub.th) can vary from approximately 1 Volt to 2.5 Volt or higher depending on the degree of the body effect of the transistor, which varies from process to process. VBST typically is the same as VDD, When VDD is less than 3 V, the term VBST*C/(C+C.sub.s) is very close to V.sub.th. As already mentioned, this will severely degrade the pumping efficiency of the multiplier. Thus, the prior art tried to eliminate V.sub.th or its effect to obtain a larger gain, e.g. to get higher VBST on the gate of the transistors N, or to use multi-phase clock signals.
The voltage diagrams presented in FIG. 1C prior art depict three internal node voltages (V1, V2, and V3 at N1, N2, and N3 respectively) during operation of the voltage multiplier circuit of FIG. 1A prior art driven by the complementary clock signals BSTA and BSTB shown in FIG. 1B prior art under some premises: all forward diode voltage drops equal (V.sub.th), all stray capacitances are neglected, no load current is drawn from output node 29 with voltage VPP. The circuit from FIG. 1A prior art can provide a supply voltage minus threshold voltage as node voltage V1=(VDD−V.sub.th) to node N1. An increase at each stage of (.DELTA.V)=VBST is obtained. If VBST=VDD the voltage increment (.DELTA.V) reaches VDD. The output voltage VPP of the circuit can thus attain VPP=V1+3* (.DELTA.V−(V.sub.th))=(VDD−V.sub.th)+3* (.DELTA.V−(V.sub.th)). However, the amplitude VBST of clock pulses BSTA and BSTB, pump capacitance (C) of capacitors C1, C2, and C3, parasitic stray capacitance (Cs), and load current are factors that can limit the voltage gain achieved at each pump stage. Thus (.DELTA.V) is the voltage increment reached under these constraints. For a capacitor charge to be passed fully from a lower stage to a higher stage, the increase in voltage for the stage (.DELTA.V) must be greater than the transistor threshold voltage (V.sub.th), the forward diode drop voltage.
Notes:
V1, V2, and V3 are the pre-boost voltage levels of nodes N1, N2, and N3 respectively. V1+(.DELTA.V), V2+(.DELTA.V), and V3+(.DELTA.V) are the post-boost voltage levels of nodes N1, N2, and N3 respectively.
The circuit in this prior art scheme of FIG. 1A prior art has a number of disadvantages, some have been already mentioned above. Five major drawbacks shall be listed in the following:                First, its charge sharing process is not completely executed, which is owed to the threshold voltage of the diode connected MOS transistor, i.e. there is always one forward diode drop voltage difference between two adjacent charge sharing nodes, which thus reduces efficiency. In other words an internal voltage value of at least one threshold voltage drop higher than the desired output voltage must be generated.        Second, owed again to said threshold voltage drop we need more CP-stages connected in series to achieve a certain target voltage up to which we want the charges to be pumped to. The more CP-stages are connected in series the less pumping efficiency is obtained, or in other words, extra stages are required to reach said certain target voltage due to this lowered efficiency.        Third, owed to the body effect the threshold voltage of higher order CP-stage's will gradually increase. It is well known, that the body effect to which integrated NMOS transistors are subject to, will increase the threshold voltage of this NMOS transistor itself. This will also limit the number of serially connected CP-stages and thus a possible higher voltage generation, because said increased threshold voltage may be higher than the available external supply voltage VDD, especially in future very low VDD voltage supply applications. If the threshold voltage of diode connected NMOS transistors is higher than the boost voltage VDD, the NMOS diode cannot be turned on and no charge sharing process will be executed. In other words, when it comes to low supply voltage levels the circuit does not perform well.        Fourth, the charge sharing speed is rather slow because the diode-configured NMOS transistors are always working in saturation region. It is well known that the effective resistance of NMOS transistors in saturation region is very large. This will increase the charge sharing time and also reduce the magnitude of the pump current within the CP because the value of the CP's settlement current is reciprocal to the charge sharing time, i.e. the time during which two capacitors are connected together.        Fifth, the breakdown voltage of the diode connected MOS transistors must increase as CP output voltage increases, which signifies that the higher order MOS transistors oxide stress is gradually increased, which will decrease the rise time of the pumping circuit and also degrade reliability. It would be desirable to have a CP circuit that can efficiently develop a high positive or negative output voltage from a low input voltage without requiring higher breakdown voltage transistors.        
At lower power supply voltages, the diode drop voltage lost within each CP-stage significantly affects the final output voltage achievable by such a CP circuit. Consequently, other approaches to design voltage multiplier circuits replace the diode type charge transfer device with a Charge Transfer Switch (CTS) device in each CP-stage. Additionally multi-phase control signal schemes are used, to more effectively control the pumping process. It is also desirable to more accurate control the CTS to reduce the forward voltage drop across the CTS when turned on to transfer charge from input to output, and to carefully control the time that the CTS is turned on to prevent back transfer of charge from output to input. A variety of solutions are found in the prior art for controlling a CTS device in attempt to simultaneously achieve these two competing goals. Nevertheless, additional improvements in CP circuits are desired. Moreover, such voltage generator circuits also may consume a significant amount of power relative to the remainder of the circuit, and thus increase the current that must be supplied by the user (e.g. by the VDD power supply). Consequently the unwanted increase in power dissipation increases the temperature of the die during operation. In a battery-powered environment, any increase in power consumed by a device has significant implications for battery life, and any additional heat generated is also more difficult to dissipate. Therefore continued improvements in CP circuits are needed. It is therefore a challenge for the designer of such circuits to achieve a higher efficiency solution. There are various patents referring to such solutions.
U.S. Pat. No. 5,886,887 (to Jenq) presents a voltage multiplier with low threshold voltage sensitivity including a voltage multiplier having a number of electrically-like stages. Each of the stages receives two input signals and a pump signal, whereby the stage has an MOS transistor with a first source/drain region and a second source/drain region and a gate. Each stage also has means for receiving a pump signal and for separately pumping the first source/drain region and the gate of the first transistor by the pump signal. The two input signals are supplied to the first source/drain region and the gate of the first transistor, respectively. A first output signal is supplied from the second source/drain region of the first transistor, and from the first source/drain region of the first transistor. A voltage signal is supplied as the input signal of the first stage and a clock signal having a first phase is supplied to the first stage as the pump signal of the first stage. The first and second output signals of the first stage are supplied to the second stage as the input signals of the second stage and a clock signal having a second phase different from the first phase is supplied to the second stage as the pump signal of the second stage.
U.S. Pat. No. 6,501,325 (to Meng) discloses low voltage supply higher efficiency cross-coupled high voltage charge pumps including an apparatus comprising a number of cross-coupled charge pump stages configured to generate an output voltage in response to (i) a supply voltage, (ii) a first signal, and (iii) a second signal, where the output voltage has a greater magnitude than the supply voltage.
U.S. Pat. No. 6,734,717 (to Min) describes a charge pump circuit which includes a first switch for connecting an input terminal to a first pumping node, a first pumping capacitor for boosting up a voltage level of the first pumping node in response to a first control signal, a second switch for connecting the first pumping node to an output terminal, a third switch for connecting the input terminal to a second pumping node, a second pumping capacitor for boosting up a voltage level of the second pumping node in response to a second control signal, and a fourth switch for connecting the second pumping node to the output terminal. The charge pump circuit decreases a loss of an output voltage and prevents malfunctions in MOS devices by preventing damages of gate oxides of the MOS devices due to excessively high voltage differences.
U.S. Pat. No. 7,023,260 (to Thorp et al.) teaches a charge pump circuit incorporating corresponding parallel charge pump stages and method therefore wherein an improved charge pump circuit efficiently utilizes multiple charge pump stages to produce output voltages much larger than the power supply voltage by incorporating, in some embodiments, two parallel strings of series-coupled charge pump stages. Each corresponding charge pump stage in one string is controlled at least by a node in the corresponding charge pump stage of the other string.
In the prior art, there are different technical approaches for achieving the goal of a higher efficiency operation for integrated voltage generator circuits. However these approaches use often solutions, which are somewhat technically complex and therefore also expensive in production. It would be advantageous to reduce the expenses in both areas.
Although the above-mentioned patents describe circuits and/or methods close to the field of the invention they differ in essential features from the circuit, the system and especially the method introduced here.